AVR140 harman/kardon
from either an external microcontroller or through3.2 Termination Requirements
one of the boot procedures listed in Section 8.
The CS49400 incorporates open drain pins which
must be pulled high for proper operation.
3. TYPICAL CONNECTION DIAGRAMS
FINTREQ and INTREQ are always open drains
Four typical connection diagrams have been
which requires a pull-up for proper operation.
presented to illustrate using the part with the
Due to the internal, multiplexed design of the pins,
different communication modes available. They
certain signals may or may not require termination
are as follows:
depending on the mode being used. If a parallel
Figure 27, "SPI Control with External Memory -
host communication mode is not being used, all
144 Pin Package" on page 38.
parallel control pins must be terminated or driven
?
Figure 28, "IntelParallel Control Mode - 144 Pin
as these pins will come up as high impedance
Package" on page 39.
inputs and will be prone to oscillation if they are
?
Figure 29, "MotorolaParallel Control Mode - 144
left floating. The specific termination requirements
Pin Package" on page 40.
may vary since the state of some of the GPIO pins
The following should be noted when viewing thewill determine the communication mode at the
typical connection diagrams:rising edge of reset (please see Section 6 ?Control?
Note:Thepinsaregroupedfunctionallyineachon page 41 for more information). For the explicit
of the typical connection diagrams. Please betermination requirements of each communication
aware that the CS49400 symbol may appear
mode please see the typical connection diagrams.
differently in each diagram.
Generally a 3.3k Ohm resistor is recommended for
The external memory interface is supportedopen drain and mode select pins. A 10k Ohm
when a serial or parallel communication mode
resistor is sufficient for all other unused inputs.
has been chosen.
3.3 Phase Locked Loop Filter
3.1 Multiplexed Pins
The internal phase locked loop (PLL) of the
The CS49400 incorporates a large amount of
CS49400 requires an external filter. The topology
flexibility into a 144 pin package. The pins are
of this filter is shown in the typical connection
internally multiplexed to serve multiple purposes.
diagrams. The component values are shown below.
Some pins are designed to operate in one mode at
Care should be taken when laying out the filter
power up, and serve a different purpose when the
circuitry to minimize trace lengths and to avoid any
DSP is running. Other pins have functionality
high frequency signals. Any noise coupled onto the
which can be controlled by the application running
filter circuit will be directly coupled into the PLL,
on the DSP. In order to better explain the behavior
which could affect performance.
of the part, the pins which are multiplexed have
been given multiple names. Each name is specificReference DesignatorValue
to the pin?s operation in a particular mode.C12.2uF
In this document, pins will be referred to by theirC21200pF
functionality. Section 12 ?Pin Description? onC368pF
page 86 describes each pin of the CS49400 and listsR13k Ohm
all of its names. Please refer to this section when
Table 1. PLL Filter Component Values
exact pin numbers are in question.
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ACEC
